DISEÑO Y CONSTRUCCIÓN DE UN ACCESO DIRECTO A MEMORIA UTILIZANDO EL LENGUAJE VHDL Y LOS DISPOSITIVOS FPGA: UNA REVISIÓN SITEMÁTICA DE LITERATURA

Oscar Cumbicus Pineda; Dayanna Alvarado Castillo; Josué Ortega Jaramillo

DISEÑO Y CONSTRUCCIÓN DE UN ACCESO DIRECTO A MEMORIA UTILIZANDO EL LENGUAJE VHDL Y LOS DISPOSITIVOS FPGA: UNA REVISIÓN SITEMÁTICA DE LITERATURA

Autores/as

Oscar Cumbicus Pineda Universidad Nacional de Loja
Dayanna Alvarado Castillo Universidad Nacional de Loja
Josué Ortega Jaramillo Universidad Nacional de Loja

Palabras clave:

FPGA, HDL, Arquitectura de computadoras

Resumen

El presente trabajo es una revisión sistemática de la literatura es el resultado de un trabajo previo para la construcción de un Acceso Directo a Memoria (DMA) utilizando el lenguaje de descripción de hardware VHDL, los dispositivos Field-programmable gate array (FPGA) y algunos algoritmos para la programación de estos dispositivos, el objetivo principal de este estudio es proporcionar una metodología eficaz para modelar el controlador de la DMA asegurando un acceso adecuado a los datos optimizando los recursos para cada una de las transacciones relevantes, otro objetivo es conocer las diferentes arquitecturas que existen y la configuración de los dispositivos para una implementación mucho más simple y óptima, la investigación literaria incluye un marco de referencia del proceso de Revisión Sistemática de la Literatura sobre estudios primarios centrados en la búsqueda de artículos relacionados con la arquitectura, el diseño y los algoritmos utilizados para construir el Controlador DMA utilizando FPGA y VHDL. Los resultados de la revisión muestran que hay una gran variedad de arquitecturas DMA, el uso de las mismas depende del tipo de transmisión que se quiera realizar y de los tipos de datos involucrados en la transacción, también hay varios modelos de diseño en múltiples lenguajes de programación y modelado, de acuerdo con la arquitectura de la DMA, existe la arquitectura mejorada del controlador que ayuda en gran medida a reducir la latencia de procesamiento, así como la presencia de una arquitectura específica necesaria para la lectura/escritura de imagen y vídeo

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Citas

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