Implementación de un Codificador y Decodificador Reed Solomon (204,188) en una Tarjeta FPGA con el Algoritmo de Euclides Modificado

Abstract

This article performs an analysis of the Reed-Solomon code theory, and then specifically describes the coding and decoding of the Reed-Solomon code (204, 188) in VHDL. After that, the code described in the Virtex 5 XUPV5-LX110T FPGA card was implemented. The encoder design was made using its generic architecture, while the decoder was used as the basis of the algorithms of Euclid Modified, Chien and Forney. Finally, the correct operation was verified and the amount of resources used on the card was determined when implementing the studied algorithm.